Re: gEDA-user: Spice netlister

["a r" <nbs.public@xxxxxxxxx>]

On Jan 20, 2008 6:19 PM, John Doty <jpd@xxxxxxxxxxxxx> wrote:
>
> On Jan 20, 2008, at 6:51 AM, a r wrote:
> > 1. It forces me to add a simulation card to the schematic. In general
> > cases that something I'd like to avoid (it is OK for testbench
> > schematics, though).
>
> I don't see why that's a big deal.

- clean schematics are needed for LVS,
- different simulators are used.

> > 2. All nested models or ".include" cards (if "-I" option was used) are
> > added inside the .subckt. That may cause problems with spice
> > simulators that do not like such nested constructs.
>
> Indeed, that's an annoyance, not only for simulation but for layout.
> The layout contractor I work with wants to see each cell in the
> netlist exactly once, at top level, not nested. But a little
> postprocessing gets the job done here.
>
> > 3. There are special "spice-subcircuit-IO" components used for making
> > subcircuit pins. Does it mean the netlister cannot cope with "normal"
> > instance pins?
>
> There are a couple of different ways to do hierarchy. If you use
> source= to associate the symbol to its subcircuit, you use the
> symbols in the "io" library to make your connections in the
> subcircuit schematic. In this case, the netlister expands all
> hierarchy automatically, making a flat netlist.
>
> On the other hand, if you use the model-name= attribute to make the
> association, you need to use the spice-subcircuit-IO symbols in the
> subcircuit schematic. In this case, you won't get a flat netlist, but
> if you also use the file= attribute you'll get a nested hierarchical
> netlist, which I don't find terribly useful.

I would prefer using "source=" attribute. As I mentioned in the other
thread I like this concept (except for current library search
strategy). Also, I would like standard (BTW, are they "in"/"out" or
"input"/"output"?) pins instead of that spice specific pins.

> One of the difficulties is that SPICE pin associations are by pin
> order (pinseq=), not by name. If you're importing a macromodel or
> cell from outside the gEDA world, you won't even have a subcircuit
> schematic.

All EDA tools I know use pin numbering just for the sake of
interfencing with external files (spice/verilog/vhdl netlist etc.).
Often this pin numbering can be automatically retrieved from the
netlist. This, in most cases, is not an issue if a schematic view is
available.

> It would be nice to be able to suppress the automatic netlist
> flattening that gnetlist does, giving the back end the option of
> creating a hierarchical netlist in the source= case.

I agree.

-r.


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