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Re: gEDA-user: gnucap questions



al davis wrote:
the netlister should put
> statements on one line for readability.
> 

OK.   I'll look at the scheme code for that.

> Other than that ...
> 
>> module verilog_io (
>>         GND ,
>>         C ,
>>         A
>>        );
>>
>> /* Port directions begin here */
>> inout GND ;
>> inout C ;
>> inout A ;
> 
>> /* Wires from the design */
>> wire B ;
>> wire GND ;
>> wire C ;
>> wire A ;
> 
> Future:
> 
> wire == digital signal.
> 
> Correct syntax, but a type mismatch.
> It should be "electrical".
> 
> For now:
> 
> Just delete that line.

Do you mean, should be
electrical B ;
electrical GND ;
?


> 
>> /* continuous assignments */
>>
>> /* Package instantiations */
>> \cap-va  C1 (
>>      .\1  ( B ),
>>      .\2  ( GND )
>>      );
> 
> The value is not specified.
> 
> There is no supplied device "\cap-va".  That's ok if you define 
> it somehow.

Can models like cap-va.va be in separate files, or should they be in the same file as the rest of the netlist?
It seems including those files in the netlist might be simplifying, but would need more scheme coding now, and
copying them as files is easy but might make clutter...  make clean could clean up the clutter.

> 
> The node names for the device "capacitor" are "p" and "n".
> 
> Similar for inductor and resistor.
> 
> It should be:
> 
> capacitor #(.c(1u)) C1 (.p(B), .n(0));

It looks like the \'s in the gnetlist -g verilog output are not wanted, is that correct?
Also, all should be on one line again...
#(.c(1u)) is completely missing as the verilog scheme code is now...

Can the device model below fit in as is?

module cap (p, n);
     (* desc="Capacitance", units="Farads" *)
     parameter real c=0 from [0:inf);
     inout p, n;
     electrical p, n;

     analog
	I(p,n) <+ c * ddt(V(p,n));
endmodule

> 
> You didn't ask, but Verilog mode uses "SI" units, not "Spice" 
> units.  1M is 1 meg.  1m is 1 milli.

Yes.  Saw that in the verilog-ams lang. ref. manual.

John Griessen


-- 
Ecosensory   Austin TX



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