Re: gEDA-user: gnucap questions

[al davis <ad151@xxxxxxxxxxxxxxxx>]

On Thursday 22 January 2009, John Griessen wrote:
> I've made a little library of devices with IO pins with pin
> labels p and n.   I get a netlist with pin numbers 1 and 2. 
> I also have model files with same first part as placed
> devices then a .va extension --  cap-va.va
>
> I'm thinking of changing to p and n pin numbers.  Any other
> suggestions before using with gnucap?
>
> How close is this example netlist to loading in gnucap?
> ----------------------------------
Gnucap verilog mode doesn't yet accept statements split across 
lines.  That will be fixed.

Even when that is fixed,I still think the netlister should put 
statements on one line for readability.

Other than that ...

> module verilog_io (
>         GND ,
>         C ,
>         A
>        );
>
> /* Port directions begin here */
> inout GND ;
> inout C ;
> inout A ;

> /* Wires from the design */
> wire B ;
> wire GND ;
> wire C ;
> wire A ;

Future:

wire == digital signal.

Correct syntax, but a type mismatch.
It should be "electrical".

For now:

Just delete that line.


> /* continuous assignments */
>
> /* Package instantiations */
> \cap-va  C1 (
>      .\1  ( B ),
>      .\2  ( GND )
>      );

The value is not specified.

There is no supplied device "\cap-va".  That's ok if you define 
it somehow.

The node names for the device "capacitor" are "p" and "n".

Similar for inductor and resistor.

It should be:

capacitor #(.c(1u)) C1 (.p(B), .n(0));

You didn't ask, but Verilog mode uses "SI" units, not "Spice" 
units.  1M is 1 meg.  1m is 1 milli.




_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user