gEDA-user: verilog-ams netlisting from gschem so gnucap can run it

[John Griessen <john@xxxxxxxxxxxxxx>]

I've gotten the gnetlist scheme backend from Mike Jarabek, gnet-verilog.scm, changed some so statements come out
in one line for readability, and have read up on verilog-ams.   It seems to put the usual values
we have on a schematic, value=1K, for instance into a simulation, you use a feature of verilog-ams
that is not generated now by gnet-verilog.scm.  You have a verilog statement that instantiates a verilog module,
creating a level of hierarchy, where the placed module can be more wiring and placements inside, or a behavioral model (called 
signal flow system in verilog-ams), or a structural model, (called conservative system in verilog-ams).  If the placed
module is a model, you can override its parameter values, and that's where we want to put in the value=1000 data from our schematics.

Here's a placed resistor statement, (inside of the top module of a verilog netlist -- see the whole thing below)

res R1 ( .n(B), .p(A));

It has no value associated.

What I am thinking is to take value from schematic placements as meaning "the main parameter",
like r = resistance, c = capacitance, etc. and apply that with what is called "parameter value assignment by order" in 
verilog-ams.  Then the above statement instantiating a resistor model would look like:

res #(1000) R1 ( .n(B), .p(A));

This gets the data, 1000, from an attrib on R1 of the schematic, value=1000 without knowing it replaces parameter
r = 0, the default r value for the resistor model, with r = 1000.  There's no need to know the first parameter name, and
we can generate netlists from plain ordinary schematics or sections of schematics originally aimed at pcb production.

John Griessen







==========================================================
module verilog_io (    GND ,    C ,    A  );

/* Port directions begin here */
inout GND ;
inout C ;
inout A ;


/* Wires from the design */
electrical B ;
electrical GND ;
electrical C ;
electrical A ;

/* continuous assignments */

/* Package instantiations */
cap C1 ( .p(B), .n(GND));

ind L1 ( .n(C), .p(B));

res R1 ( .n(B), .p(A));

endmodule


-- 
Ecosensory   Austin TX


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