Re: gEDA-user: gEDA flow for chip design?

[Patrick Doyle <wpdster@xxxxxxxxx>]

Hello Florian,
I wish I could say that I could help, but instead I'd like to say "I
too am interested in learning what's involved in using gEDA for chip
design."

I'm not even sure where to begin, other than to share the few things
I've thought about so far (however naive or clueless those thoughts
may be).

In no particular order...
I think it would be nice if I could open up existing Cadence designs
(Open Access versions) in gschem.  To that end, I have signed a
license agreement with Si2 to gain access to the OA documentation and
API and have gotten shell shocked by the fact that the OA tutorial is
over 1000 pages long.  I'm not sure if I've bitten off more than I can
chew or not.

I think it would be nice if I could run some transistor level chip
sims with gnucap.  Being a digital guy, I have absolutely no idea
what's involved in doing that, except to assume that there are other
folks (folks at Analog Rails come to mind) who must know more about
this than I ever will.

I have no idea where to start on the backend -- generating a layout.

--wpd


On Sat, Jan 15, 2011 at 11:52 AM, Florian E. Teply <usenet@xxxxxxxxxx> wrote:
> Hi folks,
>
> I seem to recall that some guys here use gEDA for chip design. John
> Doty comes to mind, but i think there are others too. I'd be interested
> in the workflow as i will have to make up some clever test chips in the
> next few years for PhD work and i'm not in the position to be able
> to sell my grandma for a full-fledged cadence seat, nor am i willing to.
>
> If reasonably possible, i'd want both simulation as well as generation
> of production-ready data (GDS or OASIS files, preferably OASIS), but
> have not the slightest idea on how to accomplish that or even if that's
> possible with open source software, let alone from whithin gEDA.
>
> Any suggestions?
>
> Thanks,
> Florian
>
>
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