gEDA-user: gEDA flow for chip design?

["Florian E. Teply" <usenet@xxxxxxxxxx>]

Hi folks,

I seem to recall that some guys here use gEDA for chip design. John
Doty comes to mind, but i think there are others too. I'd be interested
in the workflow as i will have to make up some clever test chips in the
next few years for PhD work and i'm not in the position to be able
to sell my grandma for a full-fledged cadence seat, nor am i willing to.

If reasonably possible, i'd want both simulation as well as generation
of production-ready data (GDS or OASIS files, preferably OASIS), but
have not the slightest idea on how to accomplish that or even if that's
possible with open source software, let alone from whithin gEDA.

Any suggestions?

Thanks,
Florian


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