Re: gEDA-user: gEDA flow for chip design?

["David W. Schultz" <david.schultz@xxxxxxxxxxxxx>]

On 01/15/2011 10:52 AM, Florian E. Teply wrote:
> Hi folks,
> 
> I seem to recall that some guys here use gEDA for chip design. John
> Doty comes to mind, but i think there are others too. I'd be interested
> in the workflow as i will have to make up some clever test chips in the
> next few years for PhD work and i'm not in the position to be able
> to sell my grandma for a full-fledged cadence seat, nor am i willing to.
> 
> If reasonably possible, i'd want both simulation as well as generation
> of production-ready data (GDS or OASIS files, preferably OASIS), but
> have not the slightest idea on how to accomplish that or even if that's
> possible with open source software, let alone from whithin gEDA.
> 
> Any suggestions?


http://opencircuitdesign.com/index.html

It has been a while but Magic is what I used in grad school. (It outputs
CIF and GDSII but not OASIS.) Since you are in grad school you should
find the local guru/professor. They can tell you who will do the fab and
any details specific to that. They probably even have access to the
required tools.


MOSIS is popular:

http://www.mosis.com/design/flows/design-flow-scmos-kits.html


-- 
David W. Schultz
http://home.earthlink.net/~david.schultz
"Life without stock is barely worth living..." Anthony Bourdain


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