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Re: gEDA-user: gEDA flow for chip design?
On 01/15/2011 10:52 AM, Florian E. Teply wrote:
> Hi folks,
>
> I seem to recall that some guys here use gEDA for chip design. John
> Doty comes to mind, but i think there are others too. I'd be
interested
> in the workflow as i will have to make up some clever test chips in
the
> next few years for PhD work and i'm not in the position to be able
> to sell my grandma for a full-fledged cadence seat, nor am i willing
to.
>
> If reasonably possible, i'd want both simulation as well as
generation
> of production-ready data (GDS or OASIS files, preferably OASIS), but
> have not the slightest idea on how to accomplish that or even if
that's
> possible with open source software, let alone from whithin gEDA.
>
> Any suggestions?
I have just made my first ASIC. I used gEDA and LTSpice for the front
end. To get from gschem to Magic I wrote a gnetlist translator. I did
this by writing a small scheme back end that called into a standard C++
program to do the heavy lifting. Inside Magic I did the layout with a
crude DRC based on the process I was using. I extracted back out of
Magic and reran the extract circuit in LTSpice as my LVS checker. You
can also run a simple LVS in Magic, but I did not find that entirely
reliable.
I then use a tool call KLayout and wrote scripts in ruby (the
automation language for KLayout) to manipulate the layer data to get
the resulting files I want. Klayout can export to OASIS if you wish to
use that format. I myself used GDSII. So to summarize my flow:
gschem -> gnetlist spice-oks -> LTSpice (I use my own spice back end as
well)
For doing the designing, and then
gschem -> gnetlist magic -> C++ code -> Magic -> KLayout -> Ruby ->
GDSII
to do the layout. There is no need to use the C++ code if you are a
whiz at scheme, but I really don't like LISP. I am not anti functional
languages, I just don't like the syntax of LISP. I find it hard to
maintain and read.
Oliver
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