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Re: gEDA-user: gEDA flow for chip design?

On 01/15/2011 07:39 PM, Oliver King-Smith wrote:
I extracted back out of
    Magic and reran the extract circuit in LTSpice as my LVS checker.  You
    can also run a simple LVS in Magic, but I did not find that entirely

I'd like to hear more about this.  Are you meaning functional simulation to decide
on layout vs schematic match?  You're saying the extract
function of magic is fully reliable?


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