Re: gEDA-user: gEDA flow for chip design?

[Oliver King-Smith <oliverks1@xxxxxxxxx>]

   > I extracted back out of
   >    Magic and reran the extract circuit in LTSpice as my LVS checker.
   You
   >    can also run a simple LVS in Magic, but I did not find that
   entirely
   >    reliable.
   I'd like to hear more about this.  Are you meaning functional
   simulation to decide
   on layout vs schematic match?  You're saying the extract
   function of magic is fully reliable?
   I found the extraction from Magic to be very reliable, although getting
   the parasitics setup is hard.  You can easily remove clearly bad
   parasitics.  The LVS function in magic was a little buggy.  Tim Edwards
   has some examples from me, and he is pondering why they might be
   failing.  I reduced it to a pretty simple case.  It unfortunately also
   breaks the auto-router so you should use that with care.
   Oliver
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References

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