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Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]

On 01/15/2011 10:36 PM, al davis wrote:
Unless I massively missed something, verilog is completely

Really verilog is all in parallel, not procedural code, unless you want to put some
in with special features that are trickier to use than everyday verilog.

The basic statement of verilog is assign, which defines wires
and connectivity of busses of wires and renamings and logical
combinations of wire values...  Much like a graphical schematic.

Modules also map names in verilog, allowing reuse of subcells
with different names for wires inside them.


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