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Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]

al davis wrote:

> On Friday 14 January 2011, Kai-Martin Knaak wrote:
>> Peter Clifton wrote:
> No.  David Bisset wrote, on another list.  Peter just passed it 
> on to us.
>> >> It is intended that these will be published in Altium
>> >> format as that is the CAD package of choice for the
>> >> design process.
>> Why not geda in the first place?
> Anyone here who uses LTspice need only to look in the mirror to 
> figure that out. 

They apparently decided, to issue the schematics in geda format.
This is unlike the simulation case, where it is not intended to 
redo the simulation in gnucap or ngspice. (BTW, I switched to 
qucs lately)

> Apparently, there are some features that 
> Altium has that they consider to be important.   What are they?

That's why I asked.

>> >> However we will also explore the possibility of publishing
>> >> the files for one of the Open ECAD packages such as gEDA.
>> How would the conversion be performed?
> That's obvious.  They are waiting for us to provide a conversion 
> utility.

Unless something has dramatically changed since I last checked, altium 
file format is completely inaccessible from outside. From the inside 
you'd have to sign strict NDAs.

> Let me ask for help again. ..  Gnucap has a conversion facility

I looked at lang_verilog_in.cc
Unfortunately, my c++ is not fluent enough to read the code right away.  
This is aggravated by the lack of comments on what the various code 
blocks do. Since I also don't know verilog by heart, the whole file 
looks more like a puzzle. Sorry, but this fruit is hanging too high for 
me. (You can call me programming coward)
Is there a comprehensive specification, what gnucap expects to get from 
the import plugin? If so, it might make a gschem import component a lot 
> based on Verilog syntax.  If someone writes a plugin for geda 
> format (which I have already asked for), and someone else writes 
> one for Altium format, we have that translator.

I don't see how this could possibly work. Both, gschem and altium 
contain a graphical representation of the circuit. Unless I massively 
missed something, verilog is completely procedural. Graphics 
information would be lost during the process.

Kai-Martin Knaak
Email: kmk@xxxxxxxxxxxxxxx
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