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Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]

On Saturday 15 January 2011, Kai-Martin Knaak wrote:
> I don't see how this could possibly work. Both, gschem and
> altium  contain a graphical representation of the circuit.
> Unless I massively missed something, verilog is completely
> procedural. Graphics information would be lost during the
> process.

Yes .. you missed something.  Verilog has a structural part too, 
which is well documented, has a published standard, and 
completely adequate for this.

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