[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Saturday 15 January 2011, Kai-Martin Knaak wrote:
> I don't see how this could possibly work. Both, gschem and
> altium contain a graphical representation of the circuit.
> Unless I massively missed something, verilog is completely
> procedural. Graphics information would be lost during the
> process.
Yes .. you missed something. Verilog has a structural part too,
which is well documented, has a published standard, and
completely adequate for this.
_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user