On 01/16/2011 10:09 AM, al davis wrote:
You are thinking of the original Verilog, as it was in its first draft from Cadence over 20 years ago.
Heh! You have me dated Al. That's when I was using Cadence's Verilog-XL the most. All I was getting at is the core meanings of verilog are not procedural, but parallel actions like assign. The only circuit simulation I've done lately is with gnucap. JG _______________________________________________ geda-user mailing list geda-user@xxxxxxxxxxxxxx http://www.seul.org/cgi-bin/mailman/listinfo/geda-user