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Re: gEDA-user: Soft and Hard symbols

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Am 07.01.2011 20:21, schrieb Kai-Martin Knaak:
> Colin D Bennett wrote:
>> The orthogonality
>> of these three pieces (schematic, footprint mapping, and PCB layout) is
>> pleasing to me, but I have to admit that you would rarely find a need
>> to create different PCBs from the exact same schematic.  
> ack. Up to now, I _never_ had this situation in real projects. Some aspect
> of the schematic beyond footprints and packages always needs to be changed.
> On the other hand: Almost all projects need debugging and/or service. For
> this task, footprints printed on the schematic help to locate the part in 
> the layout.
>> Still, by
>> separating the footprint mapping entirely from schematic capture, you
>> can stay focused on one task at a time.
> If this is your preferred way to work, you can already do it, even with
> heavy symbols: Just ignore the footprint attribute while placing symbols.
> Use gattrib, a text editor or a script to replace dummy values of the 
> footprints in a separate step.
> The mere fact that the footprint information is contained in the schematic
> does not imply, you have to set it during schematic capture.
> ---<)kaimartin(>---


maybe a little off topic and sorry to say, but I fear the discussion
about soft/hard/light/heavy symbols is going to over-optimize a certain
step in the design flow, the overall objective should be a working
product. And to achieve that we need to put some feedback into the
design loop. Start a design with gschem --> simulate it --> get it thru
pcb --> extract physical paramaters from the layout --> OPTIMIZE* -->
feedback to gschem --> restart the loop.

I'm aware that this can't be done by one person (unless there you have
infinte time), but each process step should propagate all
knowledge/implications to the next step (wire impedance, shielding ...).

I haven't pushed gaf/pcb to these limits yet, but ... my message is: Use
any kind of inforamtion regardless where it has been gathered to be
better next time.

BTW: In my day job (chip design, and I am in a close loop with all pro's
and con's :-) ) I  had an example of just changing physical footprints:

We had a ceramic module ($$$ and a huge manufacuring turn around time)
with 4 silicon chips on it that was attached to a pcb. The footprint of
each of hte 4 chips was fixed and the board layout was fixed, too. But
to debug the 4 chips there were 2 flavours of the ceramic carrier: One
ver y costly for the engineering hardware being capable of probing all
chip interconnects and another costreuced  (smaller) without exploiting
all chip to chip interconnects.

- -- 

Mit freundlichen Gruessen

Dietmar Schmunkamp
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