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Re: gEDA-user: Soft and Hard symbols

To: kmk@xxxxxxxxxxxx, gEDA user mailing list <geda-user@xxxxxxxxxxxxxx>
Subject: Re: gEDA-user: Soft and Hard symbols
From: DJ Delorie <dj@xxxxxxxxxxx>
Date: Fri, 07 Jan 2011 22:01:19 -0500
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In-reply-to: <ig8jl7$43k$1@xxxxxxxxxxxxxxx> (message from Kai-Martin Knaak on Sat, 08 Jan 2011 03:54:23 +0100)
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References: <1294071618.3047.23.camel@xxxxxxxxxxxxxxxxx> <xnei8urm2x.fsf@xxxxxxxxxxxxxxxx> <20110106001204.3807be62@svelte> <ig7p3q$e0c$1@xxxxxxxxxxxxxxx> <20110107122012.401918fb@svelte> <1294436234.3727.15.camel@xxxxxxxxxxxxxxxxx> <ig8jl7$43k$1@xxxxxxxxxxxxxxx>
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Kai-Martin Knaak <kmk@xxxxxxxxxxxx> writes:
> (I smell the scent of a feature request ;-)

Like http://www.delorie.com/pcb/pin-mapping.html ?

That lets the designer defer slot, package, and pin assignments until
layout time.

It assumes there's a unique identifier (not the refdes!) for each
symbol, so PCB can swap/merge/assign gates across packages.


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References:
- gEDA-user: Soft and Hard symbols
  - From: Stefan Salewski
- Re: gEDA-user: Soft and Hard symbols
  - From: DJ Delorie
- Re: gEDA-user: Soft and Hard symbols
  - From: Colin D Bennett
- Re: gEDA-user: Soft and Hard symbols
  - From: Kai-Martin Knaak
- Re: gEDA-user: Soft and Hard symbols
  - From: Colin D Bennett
- Re: gEDA-user: Soft and Hard symbols
  - From: Stefan Salewski
- Re: gEDA-user: Soft and Hard symbols
  - From: Kai-Martin Knaak

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