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Re: gEDA-user: gEDA flow for chip design?

On 01/15/2011 10:52 AM, Florian E. Teply wrote:
  i'd want both simulation as well as generation
of production-ready data (GDS or OASIS files, preferably OASIS), but
have not the slightest idea on how to accomplish that or even if that's
possible with open source software, let alone from within gEDA.

Any suggestions?


I've done chip logic and layout with Cadence tools and it was at
a small start up at first -- Cadence didn't care much about our
success and we had to do all kinds of self starting to get a working
flow even though it cost tons of money.  I've not done work with
magic, http://opencircuitdesign.com/verilog/index.html , but from
asking about it on its list, it can
generate GDS2 output and you can extract capacitance from layout with it.
If you sign up for its mail list you can ask Tim Edwards, the current
maintainer and guru about feasibility for your project.

John Doty mentioned his layout is hired out, but I can't remember what tools
are used.  He's going to be your resource for simulation.

What will you make?  some kind of sensor?

John Griessen

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