Re: gEDA-user: gEDA flow for chip design?

[John Griessen <john@xxxxxxxxxxxxxx>]

On 01/15/2011 02:21 PM, Joe Chisolm - Gmail wrote:
> Hands-on: Get started in analog IC design and fab (Part 1 of 3)
>
> http://www.eetimes.com/design/analog-design/4010380/Hands-on-Get-started-in-analog-IC-design-and-fab-Part-1-of-3-

It's nice to read about what he stressed as he went after his goal.
He mentioned simulation taking the forefront and that's true -- I'd add
characterization also.  Those MOSIS runs could tell a lot with
decent test structures along with the main circuit -- structures that
don't take  a big area, but include some amplification so
you can accurately deduce some of the low level properties
of your circuitry.  Like a capacitor hooked up with some resistance
and drive transistor chain so you can feed a signal through it and
probe the response easily as a check on capacitance per area
for the process.  And long resistors with probe pads for checking R.
per area of the process.  And whatever else is crucial to your
design.

John


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