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Re: gEDA-user: gEDA flow for chip design?

On 01/15/2011 10:52 AM, Florian E. Teply wrote:
Hi folks,

I seem to recall that some guys here use gEDA for chip design. John
Doty comes to mind, but i think there are others too. I'd be interested
in the workflow as i will have to make up some clever test chips in the
next few years for PhD work and i'm not in the position to be able
to sell my grandma for a full-fledged cadence seat, nor am i willing to.

If reasonably possible, i'd want both simulation as well as generation
of production-ready data (GDS or OASIS files, preferably OASIS), but
have not the slightest idea on how to accomplish that or even if that's
possible with open source software, let alone from whithin gEDA.

Any suggestions?


Here is a EETimes article from 2009 about a guy who did a "teach myself" project. From the article intro:

... it describes how an experienced engineer undertook to teach himself analog IC design, including his planning, the tools, the sequence of events, and the actual IC fabrication process. Whether you are thinking about learning analog IC design yourself, or just want to see how you can use available resources as part of self-paced continuing education regardless of your engineering career stage, you'll find it of interest and with actionable lessons and take-away information you can use

Hands-on: Get started in analog IC design and fab (Part 1 of 3)


Joe Chisolm
Marble Falls, Tx.

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