[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: gEDA-user: gEDA flow for chip design?

On Jan 16, 2011, at 1:52 AM, Florian E. Teply wrote:

> I seem to recall that some guys here use gEDA for chip design. John
> Doty comes to mind, but i think there are others too. I'd be interested
> in the workflow as i will have to make up some clever test chips in the
> next few years for PhD work and i'm not in the position to be able
> to sell my grandma for a full-fledged cadence seat, nor am i willing to.

I basically do schematic-level design and simulation, LVS simulation, and some testing of the physical chips. The project is based at Osaka University. They send my designs out to a layout contractor (Digian). Fab is either through MOSIS or via "Cyber Shuttle" at TSMC.

The basics of the flow may be seen at http://research.kek.jp/people/ikeda/analogVLSI/. In gEDA, I turn off hierarchy expansion. I use gnetlist to create individual subcircuits under control of a Makefile. The Makefile also contains the "cat" command that assembles the complete design.

Most design time is spent in the "Simulation" subdirectory, where the schematics for the various SPICE "test fixtures" reside. Again, a Makefile encodes construction of stimulus files, makes sure the right netlists have been built, and launches ngspice, either interactively or not, depending on the simulation.

I use a slightly customized version of ngspice: it has the hspice semantics for the noise parameters used by TSMC. Unfortunately, the patch only works for the specific models TSMC provides: poor factoring of ngspice makes propagating that patch to the general case a large job.

I have created gEDA symbols for a significant part of Professor Ikeda's Open-IP library. You may obtain these at http://www.gedasymbols.org/user/john_doty/. There you may also find the associated SPICE models, published under GPL with Professor Ikeda's (enthusiastic) permission.

John Doty              Noqsi Aerospace, Ltd.

geda-user mailing list