Re: gEDA-user: gaf and verilog?

[Mike Jarabek <mjarabek@istop.com>]

mcmahill@mtl.mit.edu wrote:

> This is probably a FAQ, but.... if I create some schematics in gschem with
> lots of 74HC logic, can gnetlist produce a simulatable verilog output for
> the ckt?

This is not likely with the current Verilog back end.  It will output stuff
like ".1" for the module ports on the instantiated gates, that are not valid
Verilog port names.  I can probably add the verilog `escape' character to
invalid Verilog names if this will help.  What is done commercially for this
situtation is to use a pin number to Verilog model port mapping.  When you
use the Synopsis smart model library, `.ptm' files are provided with the
models to obtain precisely this mapping, for a given package type.  (This
happens to be really close to what one of my day jobs is...)

--
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                              Mike Jarabek
                                FPGA/ASIC Designer
  http://www.doncaster.on.ca/~mjarabek
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