RE: gEDA-user: gschem verilog in-out ?

["EATON,JOHN (HP-Vancouver,ex1)" <john_eaton@hp.com>]

That would be a great tool. I use synopsys that does have
a netlist-> schematic generator but the results are technically
correct but not what any normal human would understand. They
lack "soul".


What would be nice is a tool that:
1) reads in a netlist 

2) loads all instances from a lib and places them in order on a 
   blank sheet

3) connects a rats nest from the connections

4) allows the designer to repositon any/all instances
   without losing connectivity

5) "routes" the design using schematic rules ie: wires
    crossing at right angles don't connect unless with a
    dot. Busses and bundles are allowed.



This would really help when tyring to port old designs or
create documentation. It seems that any PCB autorouter should
be able to handle it witht the right rule set.

John Eaton
 







-----Original Message-----
From: John Griessen [mailto:john_g@cibolo.com]
Sent: Friday, July 12, 2002 9:15 AM
To: geda-user@seul.org
Subject: Re: gEDA-user: gschem verilog in-out ?


On Thursday 11 July 2002 10:12 pm, Ales Hvezda wrote:
>    gschem does not read in verilog netlists.  Though, I'm curious,
> how many people would use such a capability?  To read in various netlists
> and create schematics from them (I assume that is what the original
> author is asking for?); which btw, I imagine is not an easy thing to do.

I would use such, and with no orderliness required, just a rat's nest would
be 
a time saver when reverse engineering in preparation for a cost reduction of

an existing product...and when reusing chunks of logic that are already 
tested, but done in other tool environments than gEDA.

That kind of work is no-glamour, but type that can be sold, so as to operate

as a consultant.  Very valuable for creating more up time with which to 
develop open source apps!

John Griessen