gEDA-user: Fixing EDIF target for Iverilog

[Naohiko Shimizu <nshimizu@keyaki.cc.u-tokai.ac.jp>]

Hi, 
I investigated tgt-edif from sourceforge and fixed some problems.
I only test with verilog file which are generated with sfl2vl,
and I only test with some small logics (I can generate 6502 or
Z80 compatible CPU with this target, but I cannot have time
to check these large edif files ;-).
There may be more investigation for use without sfl2vl.
But it will be useful enough for EDA study and/or research.

The patch against iverilog-0.7 is placed on my web.

http://shimizu-lab.dt.u-tokai.ac.jp/pgm/sfl2vl/index.html

To generate edif file:

iverilog -tedif-shmz -o something.edf something.v

Cell library of this target is a virtual one which is a variant
of ATmel's library. But conversion of the library is very easy, of course.

Enjoy,

Naohiko Shimizu
-- 
Naohiko Shimizu
Dept. Communications Engineering/Tokai University
1117 Kitakaname Hiratsuka 259-1292 Japan
TEL.+81-463-58-1211(ext. 4084) FAX.+81-463-58-8320
http://shimizu-lab.dt.u-tokai.ac.jp/