Re: gEDA-user: Edif net format

[Stephen Williams <steve@xxxxxxxxxx>]

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CN wrote:
| I have a question about edif net format; I came across this when I was running Icarus
Verilog.  If this is not the right forum for this, kindly point me at the right direction.
|
| Is it legal in edif to have multiple net refereces for parts of the same net?  For
example, can the net below
|
| (net N16 (joined (portRef I1 (instanceRef U29)) (portRef Y (instanceRef U23)) (portRef
I0 (instanceRef U27)) ))
|
| be represented by two nets, with a common point:
|
| (net N16 (joined (portRef I1 (instanceRef U29)) (portRef Y (instanceRef U23)) ))
| (net N161 (joined (portRef I1 (instanceRef U29)) (portRef I0 (instanceRef U27)) ))

That's not allowed by EDIF. (At least not EDIT 2 0 0, which is what I
have the documentation for.) Icarus Verilog doesn't do that, does it?

- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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