Re: gEDA-user: Gnetlist Verilog

[Mike Jarabek <mjarabek@xxxxxxxxx>]

Hi,

On Sat, 2006-07-22 at 12:52 -0700, User Tomdean wrote:
> It looks like if I change all symbols to contain an attribute
>   VERILOG_PORTS=POSITIONAL
> the pin number will be commented out.

Correct.

> 
> I want to avoid having two symbols for everything.
> 

I am a bit confused here.  If you are after simulating TTL chip type
logic, you will still need to have models at the chip level.  using
positional parameters may cause additional difficulties if you leave
pins unconnected.  You can create a model for a TTL chip by naming it's
ports with pinnumbers, escaped of course, and just letting the verilog
simulator take care of everything else.  You don't end up with two
symbols that way.  I have often wondered if it would make sense creating
such a library for the common ttl components from scratch.  Such a beast
exists in the commercial world, but costs a fortune to use.

If you are after something like pure logic simulation with just gates
and buffers, make sure that the verilog library is in your component
path.  These symbols are for all the basic gates available in verilog.
I have created symbols for everything up to about 10 inputs, but this
limit is an artificial one on my part, you can add more inputs to the
symbols locally if you want. You will need symbols for everything else,
like flip-flops.

I have always used the verilog netlister to stitch together blocks of
hand coded verilog, and to serve as an alternate means of expressing
top-level blocks and their interconnections.

> I am looking into something to carry over positional from the top
> level schematic.
> 
> tomdean
> 
> 
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-- 
--------------------------------------------------
                              Mike Jarabek        
                                FPGA/ASIC Designer
  http://www.istop.com/~mjarabek                    
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