Re: gEDA-user: Gnetlist Verilog

[User Tomdean <tomdean@xxxxxxxxxxxxx>]

My goal is to do slot-level simulation, to use a gschem term.

I started with an existing schematic.  After jumping thru several
hoops, I am still not there.

The library for common ttl components may be more difficult than it
first appears.

Maybe the better way to go is the verilog library...  Needs some
additional components.  One question, how to handle logic families?

This is necessary, for example, the clock/count-enable inputs to a
74xx590 depends on having a realistic gate delay.  This is different
for each logic family.

   and  #GATE_DELAY (w3,t0,CEbar);
   buf  #GATE_DELAY (w4,CPC);
   nor  #GATE_DELAY (w1,w3,w4);
   nand #GATE_DELAY (t0,w1,CPC);

and, t0 is the toggle to the first counter stage.  So, it appears as
if one needs a module for each family.  I have a 74hc590.v and a
74f590.v.  Is there a way to handle this within the existing
framework?

tomdean


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