gEDA-user: [Fwd: Re: Separate Vcc voltages]

[Jonatan Åkerlind <jonatan@xxxxxxxxxxx>]

think your post got stuck in a spam filter somewhere... forwards it to
the list since I completely agree.

-------- Forwarded Message --------
> From: Magnus Danielson <magnus@xxxxxxxxxxxxxxxxxxx>
> To: geda-user@xxxxxxxxxxxxxx, jonatan@xxxxxxxxxxx
> Subject: Re: gEDA-user: Separate Vcc voltages
> Date: Fri, 13 Jul 2007 12:04:55 +0200 (CEST)
> 
> From: Jonatan Åkerlind <jonatan@xxxxxxxxxxx>
> Subject: Re: gEDA-user: Separate Vcc voltages
> Date: Fri, 13 Jul 2007 08:44:35 +0200
> Message-ID: <1184309075.4754.4.camel@localhost>
> 
> > On tor, 2007-07-12 at 23:36 -0700, Steven Michalske wrote:
> > > don't use embedded nets in symbols.
> > > 
> > > now this is my opinion,  but unless you have a tightly controlled  
> > > part library it will be difficult to properly.
> > > 
> > > 
> > > you can also add a net attribute that will override that one I think...
> > > 
> > > Steve
> > > 
> > 
> > yes, the embedded nets seems nice if you only have one Vcc/Vdd and one
> > GND. But they make life a lot more difficult when you have separate
> > supply voltages.
> 
> Which we are seeing much more of these days. I tried to make this point many
> years ago here, but the resistance was compact. The single supply idea is lost
> in modern designs. We also need separate markings for pins having the same
> voltage as their hookup to the chip and how you treat them externally makes
> big impact to the performance. When making a large complex design you *NEED*
> them separate.
> 
> > >From http://geda.seul.org/wiki/geda:scg
> > "Do not draw power and ground pins. That information will be conveyed
> > using attributes (see the netattrib document)."
> > 
> > Is this really the recommended way still? I've been designing in a big
> > commercial ASIC suite (Cadence) this spring and there you never use such
> > things as embedded nets. IMHO this makes things clearer since you have
> > full control over your nets.
> 
> Today we need full control over the power nets these days. Embedded power nets
> is a thing of the past. It surved a purpose but modern designs have different
> requirements and thus the tools must adapt.
> 
> If you make small designs like with classic TTL and CMOS chips it works and
> saves efforts, but not else. For complex devices such as Xilinx Spartan 2E
> devices (see Xilinx folder of symbols) some of the power pins are optional and
> depending on what mode the bank runs in they may be used as normal IO pins or
> one of many voltages. You can't handle that with embedded nets without alot of
> magic and let's face it, it is not worth it.
> 
> Many CPUs also have separate core and IO power etc. etc.
> 
> The basic rule is only valid for "single supply chips". Diffrential supply
> chips (say +/- 15V for an op-amp) will work most of the time, but advanced
> use even of such devices may require full control of the nets.
> 
> I have been forced to re-make symbols since I needed control of power lines.
> 
> We need to de-embedd these nets. It was a neat idea, but doesn't match well
> with modern requirements. 
> 
> Cheers,
> Magnus



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