Re: gEDA-user: [Fwd: Re: Separate Vcc voltages]

[Steve Meier <smeier@xxxxxxxxxxxxxxxxxxx>]

Jonatan,

You missed my point. One pin from the net is vissible. The other net
pins are hidden thus reducing symbol bloat.

You can have seperate nets for the core voltage, various IO voltages,
termination voltages, reference voltages etc.

But for each mostly hidden net you expose one pint. Connect that pin
then defines which net the rest of the hidden net belongs too.

This works very well. I have a board with a pair of Stratix II Altera
FPGAs up and running right now using this method.

However, I am not using standard geda I am running a custom version.

Cheers,

Steve Meier

Jonatan Åkerlind wrote:
> On fre, 2007-07-13 at 05:04 -0700, Steve Meier wrote:
>   
>> I like partially embeded nets. Large chips, even small ones might have
>> several power pins which are internally connected. Rather then bloat a
>> symbol showing all of these pins, I like to make a embeded or hidden net
>> that includes all these pins and then make one of these pins visible.
>> The netlister then has to check a symbol to see if any of the pins are
>> vissible and connected to an external net and if so then connect the
>> rest of the hidden net to the correct net.
>>
>> Steve Meier
>>     
>
> yes, this is fine if your chip has multiple pins which are internally
> connected (and the hidden net name isn't one of Vdd or Vcc or anything
> similar). The thing is when you have multiple chips requiering different
> Vdd voltages and they all have the Vdd or Vcc hidden net internally.
> Then you cannot connect separate supply voltage to them without either
> adding another attribute in the schematic or altering the symbol to make
> the supply pin show.
>
>   



_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user