Re: gEDA-user: gnetlist missing features

["John P. Doty" <jpd@xxxxxxxxx>]

Stefan Salewski wrote:
> There was some discussion about netlist generation on this list
> recently, so maybe it is a good time to speak about missing features:
>
> I have some OpAmps with power down pins (active low) in my schematics, I
> have connected an io symbol to it with an attribute like
> "net=PreAmpPD:1".
>
> If I connect this io symbol (a copy) to an other device, i.e. to a pin
> of an FPGA all is fine. Now I decide this OpAmp should be always on, so
> I make a copy of this io symbols and connect it to a (lonesome) power
> symbol with a net attribute like "net=3.3V:1". So the power symbol and
> one instance of the io symbol are connected to each other, with no
> direct connection to other real hardware. I think this will not work
> correctly, the power down pin of the OpAmp will not be connected to the
> 3.3V rail as desired.
>   

You've told gnetlist to short PreAmpPD to 3.3V. What happens then is 
undefined. My experience is that gnetlist's behavior is difficult to 
predict in such cases: sometimes it chooses one net name over another, 
and sometimes it leaves the nets unconnected. Another example is a 
subcircuit containing a short circuit between two external connections. 
The nets in the higher level schematic don't get connected. But this is 
a perfectly reasonable object when you consider that a subcircuit may 
have different implementations in different versions of a circuit whose 
higher level description doesn't change.

The question then is: what is a simple set of logical rules that should 
govern shorted nets? These should somehow capture the intuitive 
understanding the designer has when drawing such a thing. What is this? 
Is your understanding similar to mine? Are additional attributes needed 
to describe this? Will such attributes be comprehensible to the designer?

The most pressing need here is for gnetlist to detect shorts and warn 
the user of their resolution.
> It would be very nice if this would work -- I think we had a discussion
> about this problem long time ago on the list.
>
> The other topic: There are ICs with multiple power- or output pins for
> low impedances. It would be nice to allow "pinnumber=4,5,6,7" in symbols
> to indicate that this visible power pin in the schematic should indicate
> a connection to pins 4,5,6,7 of the related footprint. (My current
> solution is to make a local copy of the footprint, have "pinnumber=4" in
> the symbol and rename pads 4,5,6,7 to 4,4,4,4 in the footprint and so
> on)
>
> Best wishes,
>
> Stefan Salewski
>
>
>
>
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>
>
>   


-- 
John Doty      Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx 



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