[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: gEDA-user: verilog -> gschem



Will the gentlest backend for verilog accept symbols with the source attribute set,  like hierarchy symbols,  but making them point to Verilog source not a sch source?

Steve


On Jul 8, 2011, at 1:29 PM, <frank@xxxxxxxxxxxxxxxx> wrote:

>> -------- Original Message --------
>> Subject: Re: gEDA-user: verilog -> gschem
>> From: John Griessen <john@xxxxxxxxxxxxxx>
>> Date: Fri, July 08, 2011 9:27 am
>> To: gEDA user mailing list <geda-user@xxxxxxxxxxxxxx>
>> 
>> On 07/07/11 17:31, frank@xxxxxxxxxxxxxxxx wrote:
>>> I just need to get it into gschem format to run through
>>> gnetlist to a different netlist format.
>> 
>> There is a gnetlist backend for verilog-ams.
>> You don't need to make schematics, just learn
>> enough scheme/guile to fix up the exiting
>> gnetlist backends for verilog.
> 
> I do not need to generate a verilog netlist, they are already in
> verilog, I need to combine circuits from differnt sources for the final
> design and as gnetlist doesn't read verilog I need to get everything
> into gscheme format. This is basically the path:
> 
> Circuit elements are coming from different sources, software, etc. The
> common format we can all use is verilog so we are using that and use
> icarus verilog for logic simulation. If we can get the verilog into
> gscheme format files I can use gscheme to combine the blocks at the top
> level (which also gives us a nice top level drawing) and run the design
> through gnetlist to create a bdnet format netllist (I've got the
> gnetlist backend mostly working to generate the bdnet format netlist).
> 
> I don't care what the schematics of the files created from the verilog
> files looks like, I can create symbols for the top level and we never
> need to decend into them. I do have a library of symbols for the
> standard cells that will be used in the verilog files and can generate
> flat verilog files so I was hoping someone had or had started a script
> that can read in a flat verilog file, refer to a directory of symbols to
> reference pin locations and create a gscheme file that is correct from a
> netlist perspective. I could try to write this but am a h/w guy and only
> fair at s/w (which is real obvious when you look at my gnetlist bdnet
> backend).
> 
> 
> 
> _______________________________________________
> geda-user mailing list
> geda-user@xxxxxxxxxxxxxx
> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user