Re: gEDA-user: verilog -> gschem

[<frank@xxxxxxxxxxxxxxxx>]

> -------- Original Message --------
> Subject: Re: gEDA-user: verilog -> gschem
> From: Ouabache Designworks <z3qmtr45@xxxxxxxxx>
> Date: Fri, July 08, 2011 9:43 am
> To: geda-user@xxxxxxxxxxxxxx
> 
> 
> The only difference between that and and PCB layout program is that you
> don't care about trace width and you can cross lines without connecting
> them.

> What you need is a symbol generator ( trivial script) , and autoplacer (
> trivial
> unless you want your result to be understandable and easily routed) and
> a autorouter ( PHD project and maybe a career).
> 
> You should be able to do a script that generates a graphical rats nest that
> had all the correct connections. That should work.
> 
> 
> John Eaton

I can probably do the script but as I am not a s/w guy I was hoping that
either someone had one or had started one I could use as a starting
point. I have been looking at the gschem file format, seems very
straight forward and I created the symbols for the standard cells in the
verilog netlists. A rats nest is fine, will never edit the schematic of
any file created from the verilog file.

As no one seems to have done this I'll have to take a crack at it, seem
useful for people combining schematic & verilog and needing to pull it
all together to create a final netlist. 



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