gEDA-user: zero-clearance pads for milled/high-power boards

[<jbump@xxxxxxxx>]

People reading this list already know this, so this is mostly a post 
for people who are searching the web trying to figure out how to make 
milled or very high power/heatsinking boards in which having thermal 
clearance around pads into copper pours is unwanted, and drawing 
multiple overlapping traces isn't working well either.  (I figured this 
out by making a part incorrectly.)

If you reduce the pad clearance to zero, a copper pour will flow right 
over it.
The problem with this is A: it'll DRC like mad, because B: you can 
easily short traces/pours across pads doing this.

However, if you're careful drawing copper polygons, it makes for a 
very nice milled board.

An example: a standard part (1206) will have:
Pad[5905 -1181 -5905 1181 5118 2000 5718 "1" "1" "square"]
a zero clearance version will change that '2000' to '0'.
(to do a whole footprint in one go, "sed 's/2000/0/g' footprintname.fp 
> > newfootprintname.fp" -- with the proviso that that'll also grab any 
other "2000" in there, including "52000", so you could make a huge 
mess.)

If other people have better suggestions for how to do this I'd love to 
hear it, but I'm thrilled with how my boards are turning out now.  I'm 
running multi-amp LED drivers, and I need all the copper I can get.  
I've started a library of {partname}noclearance.fp for this purpose so 
I can choose what I need for the board fab style/application demand.



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