Re: gEDA-user: zero-clearance pads for milled/high-power boards

[Colin D Bennett <colin@xxxxxxxxxxx>]

On Thu, 28 Jul 2011 23:39:04 -0600
<jbump@xxxxxxxx> wrote:

> People reading this list already know this, so this is mostly a post 
> for people who are searching the web trying to figure out how to make 
> milled or very high power/heatsinking boards in which having thermal 
> clearance around pads into copper pours is unwanted, and drawing 
> multiple overlapping traces isn't working well either.  (I figured
> this out by making a part incorrectly.)
> 
> If you reduce the pad clearance to zero, a copper pour will flow
> right over it.
> The problem with this is A: it'll DRC like mad, because B: you can 
> easily short traces/pours across pads doing this.

If you use a small clearance on the pad rather than zero clearance
and then draw a short, wide LINE on the copper layer that covers the
entire pad, setting the JOIN flag on the line with
"SetFlag(selected, join)", then it will help avoid getting traces
shorted to the pad, at least.

Regards,
Colin


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