Re: gEDA-user: draw_binary_real??

[Ales Hvezda <ahvezda@seul.org>]

[ Ales here, I'm reposting this since majordomo didn't recognize the
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  Please note that I am not the original author. ]

-- Cut here --
From: Alex Perry <alex@qm.com>

On Sun, May 25, 2003 at 04:18:38PM -0700, cfk wrote:
>     I am not dissing iverilog in the slightest, but I do want to urge you to
> consider a couple of things.

Speaking as another user, I disagree with your suggestions.
Icarus goes to a lot of trouble to be standard compliant and,
if in doubt, to refuse to work with code rather than misbehave.
Personally, the reason why I avoid the commercial offerings is
that they tend to guess what I want them to do (usually wrong)
rather than simply throwing an error and forcing me to code right.

The purpose of all the assertions everywhere is to catch programmer
errors.  I've never hit your problem, but then I normally write code
that synthesizes directly.  My test benches are usually designed to
be convertible into logic (unless I'm desperate) because they run faster.

>     Iverilog works fine with small verilog source files. But the issue seems
> to be with larger projects. As projects get more complex, and users take
> others cores (such as the ethernet or pci cores from opencores.org), it
> seems very important to me that the synthesis tool allows a solution to
> converge.

It does.  The issue is usually, as in the previous comment you made,
previous people taking liberties with the language specification.
YMMV.