gEDA-user: Path Delay in Icarus Verilog

[Peter Kaiser <peter@xxxxxxxxxxxx>]

Hello everybody,


I got a library with modules like this:


------------------------------------

`timescale 1ns/10ps

module INLX1 (
   Q,
   A
   );

   input  A;

   output Q;

    not (n_0,A);
    buf (Q,n_0);

   specify
        specparam       Area$           = 88.32;

        specparam       FanoutLoad$A    = 0.009;

//
// path delay
//

        (A => Q) = (0.1,0.1);


   endspecify
endmodule

-------------------------------

I can't see the path delay in my simulations. Do I something wrong?


Peter