gEDA-user: Noob question involving icarus verilog, linux and FPGA's

[shogi@xxxxxxxxx]

Recently I've bought a starters kit fpga and read some documentation about
verilog. Using this knowledge I built a simple program and voila, it
worked.
But since I'm using Linux more often than the MSW, I wanted to burn the
fpga under Linux. I downloaded the manufacturer's IDE for Linux but it
happens to be a bad solution. Using the command-line tools I get a good
result, but still..... So after some browsing I came to icarus verilog
which has some interesting features. After some adjustments I wanted to
compile my program with iverilog and voila, it compiled. But then the
problems begin: After the transformation from EDIF to the manufacturer's
propriatry format I need to synthesize? my program and I get some errors:

A. When trying to synthesize the following program:

module simple( in0, out0 );
  input  in0;
  output out0;
  wire out0=in0;
endmodule

module chip_root( sw0, ld0 );
  input  sw0;
  output ld0;
  simple dut( .out0(ld0), .in0(sw0) );
  $attribute( sw0, "PAD", "xxx");
  $attribute( ld0, "PAD", "xxx");
endmodule

I get the following error:
WARNING: ... - Design contains no instances.
I tried to ignore this warning, but it's a blocker. (And I didn't
understand the EDIF file.)

B. Also, when I change the 4th line into 'wire out0=!in0' I get the
following error:
ERROR: ... - logical block 'U1' with type 'INV' could not be resolved. ...
It looks like that I need some library?

Who knows the answer to my problems?