gEDA-user: gsch2pcb refdes label error

[John Luciani <jluciani@xxxxxxxxx>]

When running gsch2pcb on a schematic that contains a hierarchical
block the components in the lower level block have incorrect refdes's
in the PCB layout. The incorrect refdes's are preceeded by a 'U?/'.

The two simple schematics and resultant PCB layout that demonstrate
the problem are listed below. The top level schematic (top-level.sch)
contains a resistor and a hierarchical block that references
bottom-level.sch. bottom-level.sch contains a capacitor.

Am I setting up the hierarchical block incorrectly?  I am using the
gEDA tools from the 20050329 CDROM.


#---------------------- top-level.pcb --------------------

# release: pcb 1.6.3
PCB("" 6000 5000)
Grid(50 0 0 1)
Cursor(10 270 3)
Flags(0x000000d0)
Groups("1,c:2,s:3:4:5:6:7:8:")
Styles("Signal,12,45,25:Power,25,65,46:Fat,50,75,52:Skinny,9,45,25")
Element[0x0 "0805" "R1" "unknown" 0 0 -7874 -10905 0 100 0x0]
(
   Pad[-3740 -393 -3740 393 5118 2000 7118 "input" "1" 0x0100]
   Pad[3740 -393 3740 393 5118 2000 7118 "input" "2" 0x0100]
   ElementLine[-7874 3937 -7874 -3937 1000]
   ElementLine[-7874 -3937 7874 -3937 1000]
   ElementLine[7874 -3937 7874 3937 1000]
   ElementLine[7874 3937 -7874 3937 1000]
)
Element[0x0 "0805" "U?/C1" "?" 0 0 -7874 -10905 0 100 0x0]
(
   Pad[-3740 -393 -3740 393 5118 2000 7118 "input" "1" 0x0100]
   Pad[3740 -393 3740 393 5118 2000 7118 "input" "2" 0x0100]
   ElementLine[-7874 3937 -7874 -3937 1000]
   ElementLine[-7874 -3937 7874 -3937 1000]
   ElementLine[7874 -3937 7874 3937 1000]
   ElementLine[7874 3937 -7874 3937 1000]
)
Layer(1 "component")
(
)
Layer(2 "solder")
(
)
Layer(3 "three")
(
)
Layer(4 "four")
(
)
Layer(5 "five")
(
)
Layer(6 "six")
(
)
Layer(7 "seven")
(
)
Layer(8 "eight")
(
)

#----------------- top-level.sch ----------------------
v 20050313 1
N 54100 49600 54100 49500 4
N 54100 50600 54100 50500 4
C 54200 49600 1 90 0 EMBEDDEDresistor.sym
[
L 54000 50200 54200 50100 3 0 0 0 -1 -1
L 54200 50100 54000 50000 3 0 0 0 -1 -1
L 54000 50000 54200 49900 3 0 0 0 -1 -1
L 54200 49900 54000 49800 3 0 0 0 -1 -1
T 53800 49900 5 10 0 0 90 0 1
device=RESISTOR
L 54000 50200 54200 50300 3 0 0 0 -1 -1
L 54200 50300 54100 50350 3 0 0 0 -1 -1
P 54100 50500 54100 50350 1 0 0
{
T 54050 50400 5 8 0 1 90 0 1
pinnumber=2
T 54050 50400 5 8 0 0 90 0 1
pinseq=2
}
P 54100 49600 54100 49752 1 0 0
{
T 54050 49700 5 8 0 1 90 0 1
pinnumber=1
T 54050 49700 5 8 0 0 90 0 1
pinseq=1
}
L 54000 49801 54100 49750 3 0 0 0 -1 -1
T 54200 49600 8 10 0 1 90 0 1
pins=2
T 54200 49600 8 10 0 1 90 0 1
class=DISCRETE
]
{
T 53900 49800 5 10 1 1 90 0 1
refdes=R1
T 54200 49600 5 10 0 0 0 0 1
footprint=0805
}
N 54100 49500 54600 49500 4
N 54600 49500 54600 50600 4
N 54600 50600 54100 50600 4
C 54800 50000 1 0 0 EMBEDDEDhblock.sym
[
L 54800 50600 60800 50600 3 0 0 0 -1 -1
L 60800 50600 60800 50000 3 0 0 0 -1 -1
L 60800 50000 54800 50000 3 0 0 0 -1 -1
L 54800 50000 54800 50600 3 0 0 0 -1 -1
]
{
T 54800 50000 5 10 1 0 0 0 1
source=bottom-level.sch
}

#----------------------- bottom-level.sch ------------
v 20050313 1
N 54800 52000 54800 52200 4
N 54800 52200 54200 52200 4
N 54200 52200 54200 51300 4
N 54200 51300 54800 51300 4
N 54800 51300 54800 51500 4
C 54600 51500 1 0 0 EMBEDDEDcapacitor.sym
[
P 54800 52000 54800 51800 1 0 0
{
T 54850 52200 5 8 0 1 0 0 1
pinnumber=1
T 54850 52200 5 8 0 0 0 0 1
pinseq=1
}
P 54800 51500 54800 51700 1 0 0
{
T 54850 51600 5 8 0 1 0 0 1
pinnumber=2
T 54850 51600 5 8 0 0 0 0 1
pinseq=2
}
L 55000 51800 54600 51800 3 0 0 0 -1 -1
L 55000 51700 54600 51700 3 0 0 0 -1 -1
T 55200 51900 5 10 0 0 0 0 1
device=CAPACITOR
T 54600 51500 8 10 0 1 0 0 1
pins=2
T 54600 51500 8 10 0 1 0 0 1
class=DISCRETE
]
{
T 54900 51900 5 10 1 1 0 0 1
refdes=C1
T 54900 51600 5 10 1 1 0 2 1
value=?
T 54600 51500 5 10 0 0 0 0 1
footprint=0805
}