Re: gEDA-user: gnetlist bug report

[John Sheahan <jrsheahan@xxxxxxxxxxxxxxxx>]

Stuart Brorson wrote:

> Is there a reason why multiple netnames on a
> single net is a good thing or solves any particular design issue?
>
>
> Stuart

This sounds like a messy one.

Hierarchical circuits can reasonable expect the same net to have 
different names.
Two different pages can expect a net to have 2 names, matched via some
interpage connecter magic.
Two developers drawing different blocks can name differently, then
connect together using some resolution function. (maybe a connecter?)
Verilog can, via assigns, also.

I have seen horribleness where an artwork puts a default (cuttable) link
in copper. (this is great for DRC)

As places that gschem can connect/netlist to support multiple a names, 
I'd have  thought it would be simpler to allow DRC to generate a 
warning, and  netlisters as appropriate  pick one (the first?) or many 
names.   Not a heap of code.

This is real even for ground. How about when a designer specifys analog 
and digital ground connect at exactly one star point?  I've yet to see a 
layout package that does that well.

john