Re: gEDA-user: gnetlist bug report

[sdb@xxxxxxxxxx (Stuart Brorson)]

> 
> Stuart Brorson wrote:
> 
> > Is there a reason why multiple netnames on a
> > single net is a good thing or solves any particular design issue?
> > 
> > 
> > Stuart
> 
> This sounds like a messy one.
> 
> Hierarchical circuits can reasonable expect the same net to have 
> different names.
> Two different pages can expect a net to have 2 names, matched via some
> interpage connecter magic.

This is an interesting point.  Gschem -- as well as ViewDraw -- treat
netnames as globals across different pages at the same level of
hierarchy.  Therefore, interpage connectors are not implemented
(AFAIK).  This is different from Orcad, say, where you need interpage
connector symbols because netnames are local to a page.

Whether you want nets to have different names on different pages is a
question.  Wouldn't it make life more confusing to have differently
named nets?  My opinion is that the software should enforce
simplicity.  That means that you shouldn't use different names on
different pages for the same net.

> Two developers drawing different blocks can name differently, then
> connect together using some resolution function. (maybe a connecter?)

Your point about two designers combining a design is interesting.  My
reactions:

1.  Having a dedicated "net connector" symbol is one way to make this
work.  However, gnetlist would need to know about this special
connector.  

2.  Perhaps designers combining two designs could just use a Perl
script to merge the net names?

3.  How many multi-engineer designs are done using gschem anyway?  I
love the program, but also know that it's not a high-end design tool
(yet).   Anyway, when I've been involved in multi-engineer designs we
usually partitioned the work through different levels of hierarchy,
not through different pages. . . . . 

(But I do appreciate that one might use certain reuse blocks at the
same level of hierarchy.  In those cases, the reuse block is often
instantiated at top level, where you can change netnames using the
reuse block's symbol.  I'm not sure if gEDA/gaf supports this . . . .) 

> Verilog can, via assigns, also.

Yeah, and this makes certain Verilog designs very hard to follow.

> I have seen horribleness where an artwork puts a default (cuttable) link
> in copper. (this is great for DRC)
> 
> As places that gschem can connect/netlist to support multiple a names, 
> I'd have  thought it would be simpler to allow DRC to generate a 
> warning, and  netlisters as appropriate  pick one (the first?) or many 
> names.   Not a heap of code.
> 
> This is real even for ground. How about when a designer specifys analog 
> and digital ground connect at exactly one star point?  I've yet to see a 
> layout package that does that well.

Yes, this is hard to do.  I usually see the DGND and AGND symbols tied
together in the schematic.  After netlisting, these get munched
together, and the layout program doesn't see the difference.
You generally have to supply the layout engineer with a drawing of
what AGND and DGND should look like.  

One way to handle this is with a special "GND_connector" symbol,
which could then netlist to a resizable piece of metal in the layout.
The layout designer would then place the GND_connector metal like any
other footprint, except that he could edit its dimensions after
placing it.  This still doesn't solve the problem of specifying what
AGND and DGND should look like; you still need to draw those. . . . .

Stuart