Re: gEDA-user: Getting symbols from ASIC libraries into gschem: one approach

[John Doty <jpd@xxxxxxxxxxxxx>]

On Jun 11, 2007, at 10:55 PM, Jeff Trull wrote:

> Hi all,
>
> I'm consulting for a small ASIC startup that is interested in  
> gEDA.  They have
> a handful of licenses for expensive commercial tools but were  
> looking for a
> low-overhead way to do some semi-custom work and asked me to  
> investigate.  I
> just went through the process of figuring out how to make symbols  
> for the
> third-party standard cell libraries they've licensed, and I thought  
> I'd share
> my experiences since I couldn't find this described on the net  
> anywhere.
>
> Among the provided views of this library are ones for Cadence's  
> Composer
> product.  It turns out Cadence supplies a tool called "edifout",  
> which will
> produce an EDIF (text) version of any cell view.  You need to supply a
> template file, which Cadence helpfully provides an example of
> (tools/dfII/samples/xlUI/edifOut.il).  I wrote a Perl script that  
> just runs
> this once for every cell in the library, although some people  
> recommend
> building a huge schematic with every cell in it, and then running  
> edifout
> just once.  With my approach you do need to generate a new template  
> file each
> time, specifying a different cell (and you want the "symbol" view).
>
> Now you have EDIF for each cell's symbol view.  From here I tried  
> to find some
> kind of public-domain parser, but everything was a dead end.  Then  
> I realized
> that EDIF looked kind of like Lisp - i.e., an "s-expression".  It  
> turns out
> there's a CPAN module for parsing s-expressions called  
> Data::SExpression, so
> I could suck in the whole file and treat it as a data structure  
> (lists of
> lists).  I did have to do a few day's worth of coding on top of  
> this to
> generate the gschem symbols - the EDIF can be complex and the vendor
> libraries are quirky.  Here are a few difficulties I encountered:

I once attempted to use EDIF as an interchange format between  
commercial tools that supported it. It was a disaster: it would have  
been cheaper to chisel the design info into stone tablets and  
translate the result by hand. But gEDA doesn't support EDIF: why try  
*that* path?

> ...
> 3) It seems like the gnetlist backends for Spice and Verilog have  
> different
> concepts of how ports (for example) are specified, and possibly  
> other things
> as well.  It's desirable to have a single schematic netlistable to  
> either
> format, but I don't think that works right now.

Be sure to use the spice-sdb netlister, not the old spice netlister.  
See http://www.brorson.com/gEDA/SPICE/t1.html.

I don't know the Verilog netlister, but I think this should be a  
solvable problem. If I were doing Verilog, I'd want to associate  
ports by name (pinlabel=) rather than position (pinseq=). This seems  
clearer and less error prone to me. SPICE can only do this by  
position, so the methods would be independent.

Other things might need tweaking, I don't know. But even this greying  
physicist whose Lisp is as rusty as the Titanic finds gnetlist back  
ends easy to work on. The gEDA project welcomes improvements.

>
> So that's what I did.  I wouldn't be surprised if there are better
> approaches - would anyone care to comment?

Symbol creation is boring, but if you keep track of time, you'll find  
it's not a big part of the job. There are some tools (tragesym,  
djboxsym, ...) in gEDA for partially automating it. I rarely draw a  
symbol from scratch in gschem: I often modify an existing symbol.

>   I'd also be interested in hearing
> from anyone else out there who's tried to apply gEDA to ASIC design.
>

I have, for one. See http://noqsi.com/images/ 
DeltaSigmaDigitization_SPIE.pdf for a description of a chip I  
designed with gEDA. I used OpenIP (http://research.kek.jp/people/ 
ikeda/openIP/) for the digital and interface blocks. Made HSPICE  
netlists, simulated with a spicepp-ngspice flow. The layout  
contractor worked from the HSPICE netlists (mine and OpenIP). The  
folks at Osaka also ran simulations in a commercial HSPICE (Tanner).  
Fab by TSMC through MOSIS.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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