Re: gEDA-user: Getting symbols from ASIC libraries into gschem: one approach

[Jeff Trull <jetrull@xxxxxxxxxxxxx>]

On Tuesday 12 June 2007 09:37:10 John Doty wrote:

...
> I once attempted to use EDIF as an interchange format between
> commercial tools that supported it. It was a disaster: it would have
> been cheaper to chisel the design info into stone tablets and
> translate the result by hand. But gEDA doesn't support EDIF: why try
> *that* path?

I'm not really using EDIF for anything other than getting the symbols out of 
the proprietary binary database and into some text thing that I can parse.  
It goes like this:

Composer .cdb file -> EDIF -> .sym

The EDIF file lives for less than ten seconds and only ever contains symbol 
info.

>
> > ...
> > 3) It seems like the gnetlist backends for Spice and Verilog have
> > different
> > concepts of how ports (for example) are specified, and possibly
> > other things
> > as well.  It's desirable to have a single schematic netlistable to
> > either
> > format, but I don't think that works right now.
>
> Be sure to use the spice-sdb netlister, not the old spice netlister.
> See http://www.brorson.com/gEDA/SPICE/t1.html.

Yes, it's great!  That's the one I've been using (slightly modified for my 
client's needs).

>
> I don't know the Verilog netlister, but I think this should be a
> solvable problem. If I were doing Verilog, I'd want to associate
> ports by name (pinlabel=) rather than position (pinseq=). This seems
> clearer and less error prone to me. SPICE can only do this by
> position, so the methods would be independent.

Actually that part is working fine already.  My main issue with the difference 
between the Spice and Verilog netlisters is that they expect different ways 
of defining IO ports.  I believe I needed to use ipad/opad cells from 
the "verilog" library to define module ports in a Verilog schematic, but 
symbols from the "io" library to define ports in a Spice schematic.  Ideally 
you could make a single schematic and netlist it either for functional 
verification (Verilog) or circuit simulation (Spice).

I also encountered what I believe is a netlisting bug in the Verilog module 
with regard to I/Os.  I haven't been able to contact the maintainer but I've 
made a fix locally and moved on.

>
> Other things might need tweaking, I don't know. But even this greying
> physicist whose Lisp is as rusty as the Titanic finds gnetlist back
> ends easy to work on. The gEDA project welcomes improvements.

I've been doing some hacking there too and it's been mostly straightforward.  
I have found it tricky to know which Scheme functions are supported, 
sometimes, though...  Not everything in the MIT Scheme manual is available to 
backend coders (is this a Guile issue?).

>
> > So that's what I did.  I wouldn't be surprised if there are better
> > approaches - would anyone care to comment?
>
> Symbol creation is boring, but if you keep track of time, you'll find
> it's not a big part of the job. There are some tools (tragesym,
> djboxsym, ...) in gEDA for partially automating it. I rarely draw a
> symbol from scratch in gschem: I often modify an existing symbol.
>
> >   I'd also be interested in hearing
> > from anyone else out there who's tried to apply gEDA to ASIC design.
>
> I have, for one. See http://noqsi.com/images/
> DeltaSigmaDigitization_SPIE.pdf for a description of a chip I
> designed with gEDA. I used OpenIP (http://research.kek.jp/people/
> ikeda/openIP/) for the digital and interface blocks. Made HSPICE
> netlists, simulated with a spicepp-ngspice flow. The layout
> contractor worked from the HSPICE netlists (mine and OpenIP). The
> folks at Osaka also ran simulations in a commercial HSPICE (Tanner).
> Fab by TSMC through MOSIS.

Thanks for the pointer!  I'll have a look.

Best regards,
Jeff Trull

>
> John Doty              Noqsi Aerospace, Ltd.
> http://www.noqsi.com/
> jpd@xxxxxxxxx
>
>
>
>
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