Re: gEDA-user: icarus for-generate support

["Matt Ettus" <boyscout@xxxxxxxxx>]

Another update...

It seems like the problem is too many signals  If I comment out a pair
of the 32-bit wide ports then everything is ok.  Doesn't matter which
ones, as long as I remove 2 32-bit buses.

Matt

On 6/18/07, Matt Ettus <boyscout@xxxxxxxxx> wrote:
> An update on this -- I think it has something to do with the
> sel_a[0:7] net.  When declared as:
>
>     wire [7:0] sel_a;
>
> Then Xilinx is ok with it, but I get an assertion in icarus.  When declared as:
>
>    wire sel_a [0:7];
>
> then Xilinx flags an error, but Icarus gives a different assertion.
>
> Matt
>
> On 6/18/07, Matt Ettus <boyscout@xxxxxxxxx> wrote:
> > Got another one for you.  I am now using the latest git version as of
> > this morning.  I get the following assertion when trying to compile
> > the attached files.  They are short, but I put them in a tarball.  The
> > code shouldn't do anything useful yet, but I believe it is
> > syntactically correct.  The code has one for-generate in it which is
> > pretty big, but straightforward.
> >
> >
> > $ iverilog -y . buffer_pool.v
> > ivl: vvp_scope.c:1086: draw_net_in_scope: Assertion `word_count == 1' failed.
> > sh: line 1: 28410 Done                    /usr/local/lib/ivl/ivlpp -L
> > -F/tmp/ivrlg26a6451cb -f/tmp/ivrlg6a6451cb
> >      28411 Aborted                 | /usr/local/lib/ivl/ivl
> > -C/tmp/ivrlh6a6451cb -C/usr/local/lib/ivl/vvp.conf -- -
> >
> > Thanks,
> > Matt
> >
> > On 6/17/07, Stephen Williams <steve@xxxxxxxxxx> wrote:
> > >
> > > Your example below is within the skills of Icarus Verilog, but
> > > there was a very recent fix for exactly this problem. According to
> > > my git logs, it was committed 6/11/2007, which is *after* the very
> > > last snapshot. So try the current git. (It should be in the present
> > > but stopped CVS as well.)
> > >
> > >
> >
> >
>


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