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Re: gEDA-user: How to divide large symbols in smaller units?

On Jun 20, 2007, at 4:29 PM, Ben Jackson wrote:

> If you allow the Quartus II tools to do their "talkback" feature  
> (sends
> design summaries to Altera) then you get free access to SignalTap  
> (equiv
> of Chipscope, which you cannot get for free).  This is huge, imo.

I didn't know that (been a couple of years since I did an Altera  
design).  That IS huge.

> All Xilinx parts want a 2.5V VCCAUX.  So you're going to need VCCIO,
> VCCINT and VCCAUX for any Xilinx part, and if VCCIO is not 2.5 (eg
> 3.3V in my project) then you need 3 voltages.  The Altera parts have
> a single core voltage.  The PLLs need an "analog supply", but it's the
> same voltage as the core and you can make it with some caps and a  
> bead.

Xilinx got beat over the head about that.  Unlike the earlier Spartan  
3 and 3E parts, the 3A and 3AN parts can use a 3.3V VCCAUX.  They  
still use a 1.2V core so you need at least two supplies.

The killer feature of the 3AN parts, of course, is the internal  
configuration EEPROM.  Lattice was there first but it's good that  
Xilinx is finally addressing the concerns of potential customers who  
don't like their IP living in an easily-cloned memory.  Hopefully,  
they'll actually ship the smallest parts sometime this year.


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