Re: gEDA-user: vias in a row

[Bob Paddock <bob.paddock@xxxxxxxxx>]

On Sat, Jun 27, 2009 at 6:08 AM, gene glick<carzrgr8@xxxxxxxxxxxxx> wrote:
> If too many vias are placed in a straight row, fairly close to one
> another - does that make a weak point on the pcb?

Yes.  APCircuits actually tells you to do this to simulate a Score Line.
35mil holes on a 50mil grid for their Proto Service.

Also a line of very small holes, ~10mil to ~42mil depending on various board
factors like board thickness etc. can be used along Tab Breakaways
so that you don't have to have a secondary sanding operation.
See IPC-7351A 3.4.8.3.

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