gEDA-user: Hierarchy help

[Ethan Swint <eswint.ramu@xxxxxxxxxxx>]

OK- I've been messing around with hierarchy for the first time, but I'm 
a bit lost.  I've got an asymmetric phase leg inverter with three 
phases, for which I was planning to use hierarchy to make updating 
components more resistant to operator error.  I have a sub-sch file and 
a symbol file and it works as it should, for which I followed the "gTAG" 
example that ships with gEDA.

My problem then comes when I try to create the PCB.  Components there 
take on the refdes "A/D?", as opposed to "A/D1", "A/D2", etc.  I did run 
across http://www.bourbonstreetsoftware.com/GEDABlocks.html, but I was 
hoping to find something a bit more automatic.  My Bing-fu and Google-fu 
have failed me, as well.

My gnetlistrc file consists of:
(hierarchy-netattrib-mangle "disabled")
(hierarchy-netname-mangle "disabled")
(hierarchy-uref-mangle "disabled")

What obvious thing (or reference material) am I missing?

Thanks,
Ethan


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