Re: gEDA-user: PCB DRC accuracy?

[Russell Dill <Russ.Dill@xxxxxxx>]

On Tue, Jun 21, 2011 at 11:23 AM, Phil Taylor <phil@xxxxxxxxxxxxx> wrote:
> On 6/21/2011 6:53 AM, Richard Rasker wrote:
>>
>> So I wonder what tolerance PCB's DRC has? I realize that 0.006 mm (6
>> micron) is a tiny distance, but it can make all the difference between
>> an accepted and rejected board -- and thus delay in the manufacturing
>> process.
>
> I wonder too. ÂI've often set my DRC clearance to 4+/-.1 mils to get it
> through Advanced Circuits 4 mil spec. ÂI would consider this a known bug.
> ÂOf course I don't know if anyone indeed knows about it.(!)
>
> The code for DRC may round up and down for mathematical precision, but
> should not be rounding but padding all 'rounded' computations in preference
> of more clearance.
>

I've always worried about this too, especially when doing a design in
metric and sending it to an imperial board house. My guess is you need
to calculate the worst case error and add that to the DRC. The
difficult part would be finding all the possible sources of roundoff.

Perhaps if you could translate the design to a mil grid with a given
precision and *then* run DRC.


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