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Re: gEDA-user: Icarus multiplier lpm

Stephen Williams wrote: 
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Tom Hawkins wrote:
| I hit a case with Icarus synthesis involving embedded
| multiplication expressions inside concatenations.  Outside
| a concat, the multiplier is synthesized to the correct
| precision.  However, inside a concat, the multiplier
| precision is doubled.  Also with this case, I find a couple
| of non-driven nexus in the netlist.
|
| It must have something to do with mulitplication, because
| addition works fine.

The motivation there was that the width of a multiplication result
is in general the sum of the widths of the operands, and in a self-
determined width context, that's what it does. Arguments of a con-
catenation are self-determined.

However, it turns out that the IEEE1364-1995 standard was overruled
by the -2001 standard which changes the rule to the width of a
multiply being figured the same way the widths of a sum are figured.
The older behavior makes much more mathematical sense, but engineers
are not always logical, and practical engineers even less so:-)


Coming from a VHDL background I would tend to agree with you.
However, I have come to appreciate the clean semantics of Verilog's
(2001) * operator.  One operation for both signed and unsigned
multiplication; even without all those $signed constructs.

-Tom


Thus, I think we can say that you've found a bug and it's time for
a test suite entry to cover it. Note that the $bits() system function
can be used to discover how Icarus Verilog would size an expression.
To wit:

~  module main;

~   reg [7:0] a, b;
~   initial
~     begin
    $display("Width of a*b = %0d", $bits(a*b));
~     end

~  endmodule // main

~  wing % iverilog foo.vl
~  wing % vvp a.out
~  Width of a*b = 16


| I originally suspected a bug in my FNF generator, but I
| confirmed the behavior with the -t fpga target as well.
|
| Any ideas?
|
| -Tom
|
| module test (a, b, x, y, z);
|   input [7:0] a, b;
|   output [7:0] x;
|   output [8:0] y;
|   output [8:0] z;
|
|   // Synthesizes an 8-bit multiplier as expected.
|   assign x = a * b;
|
|   // Synthesizes an 8-bit adder as expected.
|   assign y = {1'b0, a + b};
|
|   // Synthesizes a 16-bit multiplier.  Why not 8-bits?
|   // Also creates a couple of non sourced nexus.
|   assign z = {1'b0, a * b};
|
| endmodule
|


- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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