gEDA-user: Re: Nested for loop?

[Stephen Williams <steve@xxxxxxxxxx>]

lingwitt@xxxxxxxxxxxxx wrote:
> Nested for loops don't seem to work in iverilog.
> it would seem that only the inner loop is updated.
> 
> Consider the following:
> 
> module TestMultiplier;
> 
>     reg  signed [7:0 ] x, y;
>     wire signed [15:0] z;
> 
>     initial
>         begin
>             $dumpvars;
> 
>             for (x = -128; x < 128; x = x + 1)
>                 for (y = -128; y < 128; y = y + 1)
>                     #1 $display("%d * %d = %d", x, y, x*y);
>         end
> 
> endmodule
> 
> Here x is always -128
> 
> Any help would be appreciated.

Look more closely. What is the bit pattern for +128, in 8 bits?
What is the bit patters for -128 in 8 bits? And for extra credit,
what comes after 127 when counting in 8 bits (signed)?

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."



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