gEDA-user: Re: Nested for loop?

[Stephen Williams <steve@xxxxxxxxxx>]

ldoolitt@xxxxxxxxxxxxxxx wrote:
> On Sat, Mar 10, 2007 at 10:11:32PM -0500, lingwitt@xxxxxxxxxxxxx wrote:
>>> Nested for loops don't seem to work in iverilog.
>>> it would seem that only the inner loop is updated.
>>>
>>>    reg  signed [7:0 ] x, y;
>>>            for (x = -128; x < 128; x = x + 1)
> 
> Stop right there.  x<128 is _always_ true, since the largest
> value representable in an 8-bit signed is 127.
> 
>>>                for (y = -128; y < 128; y = y + 1)

Aw, shucks, you were too explicit! You're ruining a teachable
moment.  (Or at least a good "Doh! I'll never make that mistake
again" moment. ... having made that same mistake myself a few
lots of times.)

(Big :-) implied.)

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."



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