Re: gEDA-user: Nested for loop?

[lingwitt@xxxxxxxxxxxxx]

On 10 Mar 2007, at 10:18:41 PM, ldoolitt@xxxxxxxxxxxxxxx wrote:

On Sat, Mar 10, 2007 at 10:11:32PM -0500, lingwitt@xxxxxxxxxxxxx wrote:

Nested for loops don't seem to work in iverilog.

it would seem that only the inner loop is updated.

   reg  signed [7:0 ] x, y;

           for (x = -128; x < 128; x = x + 1)

Stop right there.  x<128 is _always_ true, since the largest

value representable in an 8-bit signed is 127.

               for (y = -128; y < 128; y = y + 1)

Same here.  I'm not sure why your code works even as well as

you suggest it does.

There may well be an Icarus bug exposed here, but your code

doesn't help things along, either.

   - Larry

Ha! 

Thank you.

It's too late to be verilogging ;-)

This fixed the problem; sorry for the nonsense.

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